The present invention relates to a redundancy technique in semiconductor memory devices.
When manufacturing semiconductor memory devices, particles (i.e., impurities such as dust) are in general apt to get mixed in a silicon device in the middle course of each process. In the thermal process, stress is caused in silicon crystal and consequently defects are apt to occur.
Such mixture of a particle or occurrence of a defect becomes a cause of a memory cell failure of a semiconductor memory device.
As for memory cell failures, there are a single bit failure in which one predetermined memory cell of a memory cell array fails, a line failure in which a plurality of memory cells belonging to one row or one column of a memory cell array fail, and an area failure in which a plurality of memory cells contained in a predetermined area of a memory cell array fails.
To a memory cell failure, a redundancy technique for repairing the failure memory cell and thereby making it function as a normal semiconductor memory device has heretofore been applied.
The redundancy technique is frequently used in semiconductor memory devices including DRAMs (dynamic random access memories). According to this technique, all bit data are retained accurately by substituting a failure memory cell by a spare redundancy memory cell. In DRAMs, for example, the redundancy technique has been adopted from the 256-kbit generation.
The redundancy technique substitutes a failure memory cell by a redundancy memory cell. The greater the number of the redundancy memory cells is, the greater the number of normal semiconductor memory devices which can be obtained, resulting in an improved manufacturing yield.
On the other hand, the generation of DRAMS advances from 256-kbits to 1-gigabits through 1-Mbits, 4-Mbits, 16-Mbits, 64-Mbits and 256-Mbits. As the memory cell size is thus reduced, the probability of failure occurrence becomes high because of fine particles which have not posed a problem until then and an increase of stress of silicon crystal caused by a high density of memory cells on the surface of the silicon crystal.
Such occurrence of failure memory cells attendant upon the advance of the DRAM generation can be reduced by the development of a cleaning technique for reducing the particles and a process for relaxing the stress of the silicon crystal.
With only the development of the cleaning technique and a new process, however, there is a limit in preventing the occurrence of a failure memory cell.
Accordingly, the redundancy technique becomes important. In repairing a failure memory cell by using the redundancy technique, a typical method for improving the repair efficiency is to increase the number of spare rows and spare columns each of which forms the repair unit.
Here, the term "spare row" means a row formed by spare redundancy memory cells extending in the row direction of the memory cell array. The term "spare column" means a column formed by spare redundancy memory cells extending in the column direction of the memory cell array.
In the 1-Mbit generation, one spare row and one spare column are provided every 256-kbits (i.e., four spare rows and four spare columns are provided in all). In the 64-Mbit generation, eight spare rows and four spare columns are provided every one Mbit (i.e., 512 spare rows and 256 spare columns are provided in all).
Thus, by proceeding the generation of DRAMs, the number of spare lines (spare rows and spare columns) increase to improve repair efficiency.
As a result of the increase of the spare lines, however, it becomes difficult and takes a long time to judge in the redundancy technique whether a failure memory cell is repairable.
In the current judgment as to whether a failure memory cell is repairable, a functional test is carried out by using a memory tester, and on the basis of information of the failure memory cell (failure bit) obtained by this memory tester, a predetermined algorithm is used.
The tester stores an algorithm to be used in the judgment as to whether failure memory cells are repairable. Under control of the CPU, the tester starts this algorithm. If as a result of the judgment as to whether failure memory cells are repairable it is determined that all failure memory cells can be repaired by the spare lines incorporated in the semiconductor memory device, processing for substituting the failure memory cells by redundancy memory cells of the spare lines is carried out.
If as a result of the judgment as to whether failure memory cells are repairable it is determined that all failure memory cells are unrepairable by the spare lines incorporated in the semiconductor memory device, this semiconductor memory device is judged to be failed.
If the number of the spare lines each serving as the repair unit is small, the algorithm for repair becomes simple and the time required for the judgment becomes short. As the number of the spare lines each serving as the repair unit, however, the algorithm for repair becomes complicated and the time required for the judgment becomes long.
In some testers in recent years, a CPU for memory tester and a CPU for redundancy analysis are provided and both of those functions are simultaneously activated to conduct the parallel processing. However, failure occurrence information for carrying out the redundancy analysis is a result obtained by a memory tester immediately preceding (in time) the function being currently carried out. It isn't that the test and the analysis are carried out at the same time and in parallel.
As the algorithm for repair becomes complicated, therefore, the time required for the redundancy analysis becomes significantly longer than the time of the memory tester. As a result, there is a possibility that the speed of the test time is constrained.
Thus in semiconductor memory devices in which failure memory cells are repaired by using the redundancy technique, an increase of the capacity of the semiconductor memory device causes an increase in the number of spare lines each serving as the repair unit. The increase in the number of spare lines complicates the algorithm for judging as to whether repair is possible and consequently the computation time becomes long and exceeds a practical test time.